iGp12 Specifications
General
Parameter | Definition |
Sampling rate | 100–510 MHz |
FIR taps | 32 |
Supported harmonic numbers | 12–5120 |
Fiducial signal | Falling edge trigger, adjustable threshold (NIM/TTL/ECL/LVDS/LVPECL) |
Minimum fiducial pulse width | One RF period (TRF) |
External trigger inputs | 2 inputs, adjustable threshold (NIM/TTL/ECL/LVDS/LVPECL) |
Minimum trigger pulse width | 2×TRF |
Data acquisition memory | 12 Msamples |
Slow analog inputs | 8 channels @ 12 bits |
Slow analog outputs | 8 channels @ 14 bits |
Digital I/O | 32 bidirectional signals, LVTTL |
High-speed ADC & DAC
Parameter | Definition |
ADC inputs | 2 (differential) |
ADC input sensitivity | 780 mV peak-to-peak (+1.8 dBm) |
ADC resolution | 12 bits |
ADC input bandwidth | 1.3 GHz |
DAC outputs | 2 (differential) |
DAC output swing | 800 mV peak-to-peak (+2 dBm) |
DAC resolution | 12–14 bits |
DAC 10/90 rise/fall time | under 350 ps |
FIR filter control
Parameter | Definition |
Coefficients | 16 bit wide in Q15 format |
Coefficient sets | 2 |
Coefficient set select | User controllable |
Shift gain | 0–7 (1–128 actual gain) |
Downsampling | 1–32 |
Control parameters
Parameter | Definition |
One-turn delay | TRF per step, up to one revolution |
ADC clock timing | 0–TRF in 10 ps steps |
DAC clock timing | 0–TRF in 10 ps steps |
Analog outputs | 8 channels |
High-speed DAC offset trim | 1 channel |
Fiducial and trigger thresholds | 3 channels |
Digital outputs | 32 general-purpose inputs/outputs |
Data acquisition controls
Parameter | Definition |
Recording memory selection | internal blockRAM or external SRAM |
Measurement trigger | internal (software) or external (hardware) |
External trigger arming | Single or after every beam data readout |
Recorded growth length | Adjustable in units of 3 samples, up to full memory length |
Hold-off before recording | In units of 3 samples, 0 to 232-1 |
Recording downsampling | 1 to 32 |
Monitoring and diagnostics
Parameter | Definition |
Clock status | RF clock missing, DCM lock |
Feedback channel status | FIR saturation |
Acquisition state machine status | Trigger arming bit |
Voltages | FPGA core supply, 3.3 V, 5 V, 12 V bulk |
Temperatures | FPGA, ambient, two ECL devices, IOC CPU |
Fan speeds | Chassis and IOC CPU |
Analog inputs | 8 slow ADC channels |
Digital inputs | 32 general-purpose inputs/outputs |
Drive signal generator
Parameter | Definition |
Output waveform | Sine, square, or DC |
Amplitude | 0 to DAC full scale |
Bunch selectability | Bunch-by-bunch drive enable mask. Allows any subset of bunches to be driven |
Frequency range, bunch-by-bunch mode | 0–FRF/2 |
Frequency sweeping | Set by sweep span and period |
Parameter | Definition |
Input voltage | 115/230 VAC |
Input current | 2/1 A |
Frequency | 60/50 Hz |
Voltage selection | Switch |
Low voltage range | 104–126 V |
High voltage range | 207–253 V |
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